1. Technical Field of the Invention
The present invention relates generally to photolithography and, more specifically, to correction of photoresist bias between isolated patterns and dense patterns.
2. Description of Related Art
Photolithography is commonly used during formation of integrated circuits on semiconductor wafers. More specifically, a form of radiant energy (such as, for example, ultraviolet light) is passed through a radiation-patterning tool (e.g. photomasks and reticles) and onto a semiconductor wafer. Conventional photomasks and reticles contain light-restrictive regions (i.e., totally opaque or attenuated regions) and light-transmissive regions (i.e., totally transparent regions) formed in a desired pattern. A grating pattern, for example, can be used to define parallel-spaced conductive lines on a semiconductor wafer. The wafer is provided with a layer of photosensitive resist material commonly referred to as photoresist. Radiation is passed through the radiation-patterning tool onto the layer of photoresist and the features of the mask pattern are transferred to the photoresist. The photoresist is then developed to remove either the exposed portions of photoresist for a positive photoresist or the unexposed portions of the photoresist for a negative photoresist. The remaining patterned photoresist can then be used as a mask on the wafer during a subsequent semiconductor fabrication step, such as, for example, ion implantation or etching relative to materials on the wafer proximate the photoresist.
A method of forming a radiation-patterning tool is to provide a layer of light-restrictive material (such as, for example, chrome) over a light-transmissive substrate (such as, for example; a fused silicon such as quartz), and subsequently etch a pattern into the light-restrictive material.
In a typical process of fabricating semiconductor circuitry, a desired circuit pattern will be designed, and subsequently a radiation-patterning tool will be formed to create the pattern. A problem in forming the radiation-patterning tool is in correlating particular pattern shapes desired in the integrated circuitry to pattern shapes utilized in the tool. Specifically, a pattern shape formed in a tool will typically not be identical to a pattern shape generated with the tool. Light passing through a reticle tends to be refracted and scattered by the chromium edges causing interference patterns. This causes the projected image to exhibit some rounding and/or other optical distortion. The problems become especially pronounced in IC designs having feature sizes near the wavelength of light used in the photolithographic process. If the transfer of the mask pattern is not correct, it may introduce variances that exceed the tolerance of the critical dimension (CD) on the wafer.
This optical distortion (also known as the proximity effect) can be compensated for, at least in part, by modifying any given feature in the opposite direction to the expected bias. Thus, a line that would otherwise come out too narrow can be drawn as wider than its true width, etc. The overall nature and scope of these corrections will vary with the particular photolithography process that is being used.
One obvious way to avoid this phenomena is to relax the design rules of the circuit such that the CDs are not at the resolution limit of the exposure tool. However, increasing CDs, yields larger die sizes. Larger die and circuit sizes have many undesirable characteristics such as high defect densities and slower circuit speeds. Also, not utilizing the exposure tool to its fullest capabilities is not a cost effective practice.
Another solution to the proximity effect is the use of optical proximity correction (OPC). OPC compensates for the proximity effect by altering the mask image such that the resulting pattern matches the desired pattern of the non-altered mask image. Optical, proximity correction involves adding dark regions to and/or subtracting dark regions from a reticle design at locations chosen to resolve the distorting effects of diffraction and scattering, for example. Typically, OPC is performed on a digital representation of a desired IC pattern. First, the digital pattern is evaluated using software to identify regions where optical distortion is apt to result. Optical proximity correction is then applied to compensate for the distortion. The resulting pattern is ultimately transferred to the reticle glass.
The OPC process is generally performed by scanning a digital version of an IC layout design to identify feature dimensions, interfeature spacing, feature orientation, etc. The scanning process may proceed across the IC layout design in a rasterized fashion to cover the entire pattern. In some IC layout designs, it may also be necessary to conduct raster scans in the two or more directions (e.g., horizontal, vertical, and one or more diagonal directions). In some cases, the OPC computations may include generating a detailed computer model of a reticle image known as a Fast Aerial Image of Mask (FAIM). This image is then itself evaluated to determine where to make reticle corrections.
However, a drawback is encountered in that the process of performing OPC on modern IC layout designs having many features can be computationally intensive. In fact, OPC can sometimes be too great for even the most advanced computational resources. Obviously, when FAIM models are used, the computational difficulty increases significantly.
Consequently, a method and apparatus are desired which eliminate the need for different photolithography masks to compensate for bias between isolated and dense mask patterns. It would also be desired that the method and apparatus eliminate the need to use more complicated design and production of OPC masks to compensate for the bias.